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MIT 6.004 Computation Structures, Spring 2017

by: MIT OpenCourseWare

Publication date: 2017

Usage: Attribution-NonCommercial-ShareAlike 4.0 International

Topics: 6.004, Computer Design, Engineering, Digital Systems

Language: English

Instructor: Chris Terman

View the complete course: https://ocw.mit.edu/6-004S17

YouTube Playlist: https://www.youtube.com/playlist?list=PLUl4u3cNGP62WVs95MNq3dQBqY2vGOtQ2

Introduces architecture of digital systems, emphasizing structural principles common to a wide range of technologies. Multilevel implementation strategies; definition of new primitives (e.g., gates, instructions, procedures, processes) and their mechanization using lower-level elements. Analysis of potential concurrency; precedence constraints and performance measures; pipelined and multidimensional systems. Instruction set design issues; architectural support for contemporary software structures.

License: Creative Commons BY-NC-SA

More information at https://ocw.mit.edu/terms

More courses at https://ocw.mit.edu

Addeddate: 2019-05-22 19:46:20

Color: color

Identifier: MIT6.004S17

Scanner: Internet Archive HTML5 Uploader 1.6.4

Sound: sound

Year: 2017

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1 file

ITEM TILE

172 files

MPEG4

BACK

5.7M

1.2.1 What is Inf1.2.1 What is Information?ormation?

6.9M

1.2.2 Quantifying Information

5.3M

1.2.3 Entropy

4.7M

1.2.4 Encoding

8.1M

1.2.5 Fixed-length Encodings

6.2M

1.2.6 Signed Integers: 2's complement

4.9M

1.2.7 Variable-length Encoding

3.1M

1.2.8 Huffman's Algorithm

2.5M

1.2.9 Huffman Code

6.7M

1.2.10 Error Detection and Correction

2.8M

1.2.11 Error Correction

3.8M

1.2.12 Worked Examples: Quantifying Information

7.3M

1.2.12 Worked Examples: Two's Complement Representation

6.7M

1.2.12 Worked Examples: Two's Complement Addition

8.4M

1.2.12 Worked Examples: Huffman Encoding

7.6M

1.2.12 Worked Examples: Error Correction

5.8M

2.2.1 Concrete Encoding of Information

9.2M

2.2.2 Analog Signaling

5.6M

2.2.3 Using Voltages Digitally

7.7M

2.2.4 Combinational Devices

5.7M

2.2.5 Dealing with Noise

6.7M

2.2.6 Voltage Transfer Characteristic

3.8M

2.2.7 VTC Example

8.7M

2.2.8 Worked Examples: The Static Discipline

10.0M

3.2.1 MOSFET: Physical View

10.2M

3.2.2 MOSFET: Electrical View

6.8M

3.2.3 CMOS Recipe

6.7M

3.2.4 Beyond Inverters

5.4M

3.2.5 CMOS Gates

11.0M

3.2.6 CMOS Timing

6.2M

3.2.7 Lenient Gates

2.8M

3.2.8 Worked Examples: CMOS Functions

4.5M

3.2.8 Worked Examples: CMOS Logic Gates

11.4M

4.2.1 Sum of Products

7.3M

4.2.2 Useful Logic Gates

8.5M

4.2.3 Inverting Logic

6.7M

4.2.4 Logic Simplification

14.6M

4.2.5 Karnaugh Maps

5.6M

4.2.6 Multiplexers

7.9M

4.2.7 Read-only Memories

7.2M

4.2.8 Worked Examples: Truth Tables

10.9M

4.2.8 Worked Examples: Gates and Boolean Logic

3.8M

4.2.8 Worked Examples: Combinational Logic Timing

6.0M

4.2.8 Worked Examples: Karnaugh Maps

12.3M

5.2.1 Digital State

8.4M

5.2.2 D Latch

7.1M

5.2.3 D Register

6.7M

5.2.4 D Register Timing

7.8M

5.2.5 Sequential Circuit Timing

4.8M

5.2.6 Timing Example

3.4M

5.2.7 Worked Example 1

4.4M

5.2.8 Worked Example 2

7.1M

6.2.1 Finite State Machines

13.7M

6.2.2 State Transition Diagrams

4.9M

6.2.3 FSM States

7.7M

6.2.4 Roboant Example

7.6M

6.2.5 Equivalent States; Implementation

12.1M

6.2.6 Synchronization and Metastability

9.2M

6.2.7 Worked Examples: FSM States and Transitions

5.4M

6.2.7 Worked Examples: FSM Implementation

8.8M

7.2.1 Latency and Throughput

8.5M

7.2.2 Pipelined Circuits

8.5M

7.2.3 Pipelining Methodology

10.6M

7.2.4 Circuit Interleaving

7.7M

7.2.5 Self-timed Circuits

3.8M

7.2.6 Control Structures

11.1M

7.2.7 Worked Examples-Pipelining

9.0M

7.2.7 Worked Examples-Pipelining 2

13.9M

8.2.1 Power Dissipation

7.6M

8.2.2 Carry-select Adders

7.4M

8.2.3 Carry-lookahead Adders

7.4M

8.2.4 Binary Multiplication

7.3M

8.2.5 Multiplier Tradeoffs

5.0M

8.2.6 Part 1 Wrap-up

6.4M

9.2.1 Datapaths and FSMs

8.9M

9.2.2 Programmable Datapaths

12.8M

9.2.3 The von Neumann Model

7.4M

9.2.4 Storage

7.8M

9.2.5 ALU Instructions

6.9M

9.2.6 Constant Operands

4.1M

9.2.7 Memory Access

8.1M

9.2.8 Branches

4.7M

9.2.9 Jumps

11.9M

9.2.10 Worked Examples-Programmable Architectures

9.6M

10.2.1 Intro to Assembly Language

6.1M

10.2.2 Symbols and Labels

11.8M

10.2.3 Instruction Macros

6.2M

10.2.4 Assembly Wrap-up

12.5M

10.2.5 Models of Computation

12.1M

10.2.6 Computability, Universality

4.3M

10.2.7 Uncomputable Functions

9.8M

10.2.8 Worked Examples-Beta Assembly

10.9M

11.2.1 Iterpretation and Compilation

10.7M

11.2.2 Compiling Expressions

5.2M

11.2.3 Compiling Statements

5.8M

11.2.4 Compiler Frontend

10.5M

11.2.5 Optimization and Code Generation

11.7M

11.2.6 Worked Examples

11.6M

12.2.1 Procedures

11.2M

12.2.2 Activation Records and Stacks

7.9M

12.2.3 Stack Frame Organization

6.8M

12.2.4 Compiling a Procedure

8.5M

12.2.5 Stack Detective

23.0M

12.2.6 Worked Examples-Procedures and Stacks

11.5M

13.2.1 Building Blocks

8.5M

13.2.2 ALU Instructions

5.9M

13.2.3 Load and Store

10.5M

13.2.4 Jumps and Branches

7.1M

13.2.5 Exceptions

4.8M

13.2.6 Summary

11.8M

13.2.7 Worked Examples-A Better Beta

15.7M

13.2.7 Worked Examples-Beta Control Signals

6.0M

14.2.1 Memory Technologies

11.3M

14.2.2 SRAM

6.5M

14.2.3 DRAM

10.7M

14.2.4 Non-volatile Storage; Using the Hierarchy

9.2M

14.2.5 The Locality Principle

7.6M

14.2.6 Caches

9.9M

14.2.7 Direct-mapped Caches

7.8M

14.2.8 Block Size; Cache Conflicts

11.8M

14.2.9 Associative Caches

7.2M

14.2.10 Write Strategies

17.6M

14.2.11 Worked Examples-Cache Benefits

14.8M

14.2.11 Worked Examples-Caches

11.5M

15.2.1 Improving Beta Performance

9.0M

15.2.2 Basic 5-Stage Pipeline

31.0M

15.2.3 Data Hazards

13.6M

15.2.4 Control Hazards

6.7M

15.2.5 Exceptions and Interrupts

3.1M

15.2.6 Pipelining Summary

13.3M

15.2.7 Worked Examples-Pipelined Beta

10.9M

15.2.7 Worked Examples-Beta Junkyard

9.3M

16.2.1 Even More Memory Hierarchy

15.4M

16.2.2 Basics of Virtual Memory

9.4M

16.2.3 Page Faults

14.3M

16.2.4 Building the MMU

6.5M

16.2.5 Contexts

10.2M

16.2.6 MMU Improvements

15.1M

16.2.7 Worked Examples-Virtual Memory

7.2M

17.2.1 Recap: Virtual Memory

11.6M

17.2.2 Processes

15.7M

17.2.3 Timesharing

16.5M

17.2.4 Handling Illegal Instructions

10.5M

17.2.5 Supevisor Calls

9.2M

17.2.6 Worked Examples-operating systems

8.8M

18.2.1 OS Device Handlers

11.7M

18.2.2 SVCs for Input/Output

8.1M

18.2.3 Example: Match Handler with OS

7.5M

18.2.4 Real Time

7.5M

18.2.5 Weak Priorities

10.7M

18.2.6 Strong Priorities

9.6M

18.2.7 Example: Priorities in Action!

8.7M

18.2.8 Worked Examples-devices and interrupts

11.5M

19.2.1 Interprocess Communication

9.7M

19.2.2 Semaphores

11.4M

19.2.3 Atomic Transactions

5.8M

19.2.4 Semaphore Implementation

10.3M

19.2.5 Deadlock

8.8M

19.2.6 Worked Examples-semaphores

11.4M

20.2.1 System-level Interfaces

13.1M

20.2.2 Wires

6.6M

20.2.3 Buses

9.8M

20.2.4 Point-to-point Communication

5.9M

20.2.5 System-level Interconnect

8.9M

20.2.6 Communication Topologies

16.0M

21.2.1 Instruction-level Parallelism

8.2M

21.2.2 Data-level Parallelism

6.6M

21.2.3 Thread-level Parallelism

8.1M

21.2.4 Shared Memory & Caches

12.7M

21.2.5 Cache Coherence

10.8M

21.2.6 6.004 Wrap-up

76.7M

An Interview with Christopher Terman on Teaching Computation Structures

172 files

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172 files

SUBRIP

BACK

3.7K

1.2.1 What is Information?

8.3K

1.2.2 Quantifying Information

3.8K

1.2.3 Entropy

4.7K

1.2.4 Encoding

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1.2.5 Fixed-length Encodings

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1.2.6 Signed Integers: 2's complement

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1.2.7 Variable-length Encoding

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1.2.8 Huffman's Algorithm

1.7K

1.2.9 Huffman Code

7.2K

1.2.10 Error Detection and Correction

2.1K

1.2.11 Error Correction

2.3K

1.2.12 Worked Examples: Quantifying Information

5.7K

1.2.12 Worked Examples: Two's Complement Representation

4.6K

1.2.12 Worked Examples: Two's Complement Addition

8.6K

1.2.12 Worked Examples: Huffman Encoding

7.7K

1.2.12 Worked Examples: Error Correction

6.9K

2.2.1 Concrete Encoding of Information

12.0K

2.2.2 Analog Signaling

7.3K

2.2.3 Using Voltages Digitally

7.8K

2.2.4 Combinational Devices

5.6K

2.2.5 Dealing with Noise

6.7K

2.2.6 Voltage Transfer Characteristic

2.5K

2.2.7 VTC Example

6.0K

2.2.8 Worked Examples: The Static Discipline

10.7K

3.2.1 MOSFET: Physical View

10.7K

3.2.2 MOSFET: Electrical View

7.0K

3.2.3 CMOS Recipe

7.2K

3.2.4 Beyond Inverters

4.4K

3.2.5 CMOS Gates

13.4K

3.2.6 CMOS Timing

6.4K

3.2.7 Lenient Gates

1.9K

3.2.8 Worked Examples: CMOS Functions

3.4K

3.2.8 Worked Examples: CMOS Logic Gates

12.4K

4.2.1 Sum of Products

9.2K

4.2.2 Useful Logic Gates

10.3K

4.2.3 Inverting Logic

7.7K

4.2.4 Logic Simplification

15.3K

4.2.5 Karnaugh Maps

4.5K

4.2.6 Multiplexers

7.5K

4.2.7 Read-only Memories

3.7K

4.2.8 Worked Examples: Truth Tables

10.5K

4.2.8 Worked Examples: Gates and Boolean Logic

2.0K

4.2.8 Worked Examples: Combinational Logic Timing

4.2K

4.2.8 Worked Examples: Karnaugh Maps

13.8K

5.2.1 Digital State

8.2K

5.2.2 D Latch

8.4K

5.2.3 D Register

9.5K

5.2.4 D Register Timing

10.9K

5.2.5 Sequential Circuit Timing

5.5K

5.2.6 Timing Example

3.5K

5.2.7 Worked Example 1

4.8K

5.2.8 Worked Example 2

9.6K

6.2.1 Finite State Machines

14.8K

6.2.2 State Transition Diagrams

5.4K

6.2.3 FSM States

7.3K

6.2.4 Roboant Example

7.8K

6.2.5 Equivalent States; Implementation

13.1K

6.2.6 Synchronization and Metastability

7.5K

6.2.7 Worked Examples: FSM States and Transitions

3.6K

6.2.7 Worked Examples: FSM Implementation

9.1K

7.2.1 Latency and Throughput

8.2K

7.2.2 Pipelined Circuits

8.1K

7.2.3 Pipelining Methodology

9.6K

7.2.4 Circuit Interleaving

8.3K

7.2.5 Self-timed Circuits

3.7K

7.2.6 Control Structures

9.1K

7.2.7 Worked Examples-Pipelining

7.2K

7.2.7 Worked Examples-Pipelining 2

19.2K

8.2.1 Power Dissipation

8.9K

8.2.2 Carry-select Adders

7.0K

8.2.3 Carry-lookahead Adders

8.2K

8.2.4 Binary Multiplication

7.0K

8.2.5 Multiplier Tradeoffs

4.3K

8.2.6 Part 1 Wrap-up

7.4K

9.2.1 Datapaths and FSMs

6.7K

9.2.2 Programmable Datapaths

17.7K

9.2.3 The von Neumann Model

9.9K

9.2.4 Storage

9.3K

9.2.5 ALU Instructions

7.2K

9.2.6 Constant Operands

4.1K

9.2.7 Memory Access

10.1K

9.2.8 Branches

4.7K

9.2.9 Jumps

9.0K

9.2.10 Worked Examples-Programmable Architectures

11.3K

10.2.1 Intro to Assembly Language

5.9K

10.2.2 Symbols and Labels

9.7K

10.2.3 Instruction Macros

6.0K

10.2.4 Assembly Wrap-up

7.5K

10.2.5 Models of Computation

7.4K

10.2.6 Computability, Universality

2.8K

10.2.7 Uncomputable Functions

6.7K

10.2.8 Worked Examples-Beta Assembly

12.7K

11.2.1 Iterpretation and Compilation

10.9K

11.2.2 Compiling Expressions

5.3K

11.2.3 Compiling Statements

5.8K

11.2.4 Compiler Frontend

10.3K

11.2.5 Optimization and Code Generation

9.6K

11.2.6 Worked Examples

13.7K

12.2.1 Procedures

11.5K

12.2.2 Activation Records and Stacks

7.9K

12.2.3 Stack Frame Organization

6.3K

12.2.4 Compiling a Procedure

7.3K

12.2.5 Stack Detective

21.9K

12.2.6 Worked Examples-Procedures and Stacks

16.2K

13.2.1 Building Blocks

9.4K

13.2.2 ALU Instructions

5.9K

13.2.3 Load and Store

9.5K

13.2.4 Jumps and Branches

9.2K

13.2.5 Exceptions

4.9K

13.2.6 Summary

10.9K

13.2.7 Worked Examples-A Better Beta

14.2K

13.2.7 Worked Examples-Beta Control Signals

6.7K

14.2.1 Memory Technologies

9.4K

14.2.2 SRAM

8.4K

14.2.3 DRAM

11.7K

14.2.4 Non-volatile Storage; Using the Hierarchy

11.7K

14.2.5 The Locality Principle

7.7K

14.2.6 Caches

9.1K

14.2.7 Direct-mapped Caches

7.8K

14.2.8 Block Size; Cache Conflicts

12.1K

14.2.9 Associative Caches

6.2K

14.2.10 Write Strategies

16.4K

14.2.11 Worked Examples-Cache Benefits

14.2K

14.2.11 Worked Examples-Caches

14.0K

15.2.1 Improving Beta Performance

9.6K

15.2.2 Basic 5-Stage Pipeline

19.0K

15.2.3 Data Hazards

17.6K

15.2.4 Control Hazards

7.0K

15.2.5 Exceptions and Interrupts

2.6K

15.2.6 Pipelining Summary

10.9K

15.2.7 Worked Examples-Pipelined Beta

11.3K

15.2.7 Worked Examples-Beta Junkyard

9.4K

16.2.1 Even More Memory Hierarchy

15.8K

16.2.2 Basics of Virtual Memory

8.5K

16.2.3 Page Faults

12.1K

16.2.4 Building the MMU

6.4K

16.2.5 Contexts

9.5K

16.2.6 MMU Improvements

12.6K

16.2.7 Worked Examples-Virtual Memory

7.4K

17.2.1 Recap: Virtual Memory

11.6K

17.2.2 Processes

13.5K

17.2.3 Timesharing

9.9K

17.2.4 Handling Illegal Instructions

8.6K

17.2.5 Supevisor Calls

8.6K

17.2.6 Worked Examples-operating systems

8.1K

18.2.1 OS Device Handlers

11.5K

18.2.2 SVCs for Input/Output

7.9K

18.2.3 Example: Match Handler with OS

7.6K

18.2.4 Real Time

7.4K

18.2.5 Weak Priorities

10.1K

18.2.6 Strong Priorities

8.3K

18.2.7 Example: Priorities in Action!

7.8K

18.2.8 Worked Examples-devices and interrupts

12.1K

19.2.1 Interprocess Communication

9.9K

19.2.2 Semaphores

11.7K

19.2.3 Atomic Transactions

5.8K

19.2.4 Semaphore Implementation

10.6K

19.2.5 Deadlock

9.3K

19.2.6 Worked Examples-semaphores

9.9K

20.2.1 System-level Interfaces

12.8K

20.2.2 Wires

6.7K

20.2.3 Buses

9.3K

20.2.4 Point-to-point Communication

6.4K

20.2.5 System-level Interconnect

8.4K

20.2.6 Communication Topologies

19.0K

21.2.1 Instruction-level Parallelism

8.9K

21.2.2 Data-level Parallelism

7.1K

21.2.3 Thread-level Parallelism

7.8K

21.2.4 Shared Memory & Caches

13.2K

21.2.5 Cache Coherence

8.1K

21.2.6 6.004 Wrap-up

60.5K

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